Job Description

Position Summary
Samsung is a world leader in Memory, LCD and System LSI technologies that has the vision and commitment to invest in the future of technology - demonstrated by the $17B investment in the new 3nm Fab in Texas and the commitment to invest in dramatically expanding design activities across GPU, System IP and SoC Architecture. We are currently looking for exceptional hardware verification engineers to join our System IP team in our Austin, TX R & D Center (SARC) and our Advanced Computing Lab (ACL) in San Jose, CA. System IP team develops proprietary coherent interconnect and memory controller IPs deployed in many high-volume products.
Role and Responsibilities
As a System IP Design Verification Contractor you will contribute to the functional verification of System IP including coherent interconnect and caches. This is a technical individual contributor role with heavily involved hands-on project execution. A strong background in Design Verification and hands-on experience with both block-level and top-level is required to be successful in this role.
Architecting and building re-usable testbenches right from scratch Proposing and driving best practices/methodologies/automation that can improve productivity Owning key features and timely execution of tasks as per milestones Experience with GLS [gate level simulation] Creating test plans as per spec and presenting to various stakeholders Working with designers to resolve any spec issues Creating test benches, verification environments, stimulus, tests Collaborating with designers to verify the correctness of a design feature, and resolve fails Developing assertions, checkers, covergroups, Systemverilog constraints Debugging and root causing functional fails from regressions Analyzing code and functional coverage results, performing gap analysis Working with SoC team to debug functional fails during IP bringup and feature execution Collaborating with Physical design teams, running and debugging gate-level simulations Collaborating with Performance verification teams to help with co-sim TB bringup Bringup power-aware verification with UPF Helping with Silicon bringup and root causing fails Skills and Qualifications
15+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 13+ years of experience with a Master's degree, or 11+ years of experience with a PhD 12+ years industry experience in a design verification role Expert hands-on coding skills in Testbench, Stimulus, checkers development, coverage closure. Experience with System Verilog, UVM or equivalent Knowledge of ARM protocols or equivalent protocols - CHI, AXI, ACElite, APB Experience with Git version control, Unix/Perl/Python scripting Good written and verbal communication skills Experience with GLS, power vector generation Formal verification skills will be a plus Combined experience with coherent interconnect, caches and LPDDR memory controllers will be a plus
Our Team
Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. Our team plays a key role in influencing the product roadmap for a market-leading system IP solutions. We focus on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem.
With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.
Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team's culture.
Total Rewards
The hourly rate range for this role is between $90 and $120 per hour. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location. Your actual hourly rate will depend on variables that may include your education skills, qualifications, experience, and work location.
U.S. Export Control
This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.
Trade Secrets
By submitting an application, you [applicant] agree[s] not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information (including trade secrets) belonging to any current or previous employer or other person or entity.
#SARC #ACL #Hybrid
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Job Tags

Hourly pay, For contractors,

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